The present invention relates to forming electrical contacts within integrated circuit structures, and more specifically to forming conductive contacts through inter-dielectric layers and including air gaps next to the conductive contacts.
Gate-to-contact parasitic capacitances in integrated circuit (IC) structures contribute to increased power consumption and reduced device performance/speed. Typical spacers formed on gate sidewalls employ silicon nitride, but silicon nitride has a relatively high dielectric constant and thus results in high gate parasitic capacitances. Oxide spacers can reduce capacitance but do not stand up well to typical processing such as silicide (HF) precleans. Nitride spacers can also be used, and later removed following silicide formation, and replaced with lower-capacitance materials (oxide, or low-K materials).